Display means including LCD are widely used in many portable electronic apparatuses such as, mobile phones personal handyphone systems (PHSs), and personal digital assistants (PDAs).
LCD used in these electronic apparatuses are increasingly equipped with a larger display panel having an increased number of tone levels in order to improve the visibility of information on the LCD. This inevitably entails greater power consumption by a display. Power saving is important for a portable electronic apparatus since it directly affects the operable hours of the apparatus if it is powered by a battery.
In order to save energy, information is displayed on a limited area of a large LCD panel (the limited area hereinafter referred to as display area), or at a limited tone level, when the entire area is not needed or the panel is not in operation or in communication with other components of the apparatus. Thus, the amount of data to be displayed by the panel is reduced in a reduced display mode to reduce the driving frequency of the panel, i.e. to prolong the period for selecting each row of the panel (the period hereinafter referred to as row selection period). A maximum possible power saving can be attained if the driving frequency is precisely lowered to an optimum power saving frequency.
FIG. 1 is a block diagram showing a conventional LCD driving device designed to operate at a lowered frequency to save power depending on the display mode selected. FIG. 2 is a timing diagram for the operation of the LCD driving device of FIG. 1.
The LCD driving device for an LCD panel 20 shown in FIG. 1 has an interface 11, a display memory 12, a display controller 33, an LCD driver 14, and a clock generator 35.
The interface 11 receives externally supplied display data, which is stored in the display memory 12.
The clock generator 35 generates a system clock SCK suitable for a specified display mode. The clock is supplied to other components including the display controller 33.
In addition to system clock SCK, the display controller 33 is supplied with information specifying a display mode which defines the display area and the tone level for the data. The display data stored in the display memory 12 is retrieved therefrom and supplied to the LCD driver 14 in accordance with the display mode. Timing of the retrieval is performed based on the system clock SCK. Under the control of the display controller 33, the LCD driver 14 determines a driving voltage for driving the LCD panel 20 based on the display data received from the display controller 33. Incidentally, the LCD driving device is formed in one chip or several chips, and is controlled by a CPU for example.
Referring to FIGS. 2A and 2B, there are shown operations of this conventional LCD driving device controlling the LCD panel 20. FIGS. 2A and 2B illustrate relationships between timings of: (a) row selection, (b) supply voltage, (c) column output, (d) system clock SCK, and (e) access to the display memory.
Row terminals (e.g. common terminal) of the LCD panel 20 are selected in sequence from the upper most one to the lowest one at a given timing (the timing will be hereinafter referred to as row selection timing). The time interval Tr1 between the two successive row selections, referred to as row selection period, as shown in FIG. 2A(a) is determined appropriately according to the number of row terminals and/or tone levels to be selected in one frame. A shorter row selection period Tr1 is required for a larger display area and/or a high tone level.
On the other hand, respective column terminals (e.g. segment terminals) of the LCD panel 20 are provided with driving voltages associated with a line of selected row terminals. The display controller 33 prepares data for the next row selection period (the data will be referred to as the next display data). This can be done by accessing the display memory 12 a number of times while the LCD driver 14 is providing the current row selection column output. For example, while driving voltages are applied to the column terminals associated with a row line i−1 as shown in FIG. 2A(c), the next display data for the next line i is sequentially retrieved from the display memory 12 by accessing the memory a number of times (indicated by upward arrows) as shown in FIG. 2A(e).
In the example shown herein the frequency of such memory access in one selection period Tr1 is 8 as shown in FIG. 2A(e). However, the frequency is actually determined by the ratio of the amount of data for one line and the amount of data that can be retrieved from the display memory 12 in one read.
In the conventional LCD driving device shown in FIG. 1, an instruction specifying the display mode is provided not only to the display controller 33 but also to the clock generator 35 so that the clock generator 35 will reduce the frequency of the clock SCK, as shown in FIG. 2B (d), when the amount of display data decreases in a reduced display mode requiring only a reduced display area and/or a lower tone level. Accordingly, in order to minimize power consumption by the LCD by reducing the frequency of selection timing (and hence the driving frequency of the LCD), a longer row selection period Tr2 is selected as shown in FIG. 2B(a).
This conventional LCD driving device requires a clock generator capable of generating a variable system clock SCK for clocking the LCD panel in reduced display modes (associated with low tone levels and partial display areas). In order to provide the clock generator with this capability, the time constant of the clock generator 35 is regulated to provide a required frequency. It is then necessary to provide means for precisely regulating the time constant (referred to as time constant regulator) of the clock generator 35 over a wide range of frequency, which is not easy.
If, however, the clock generator 35 is provided with an external time constant regulator, it is not possible to program the regulator by an internal controller such as CPU to automatically generate a desired time constant depending on different display modes. A frequency divider may be provided in a stage following the clock generator 35 for regulating the driving frequency of the LCD. However, since such a frequency divider has a frequency division ratio m, where m is an integer, it can only change the clock frequency by a factor of 1/m, failing to provide fine regulation of the driving frequency.
It should be noted that in an LCD driving device the supply voltage Vdd of a battery is temporarily lowered by the driving current activating one row of the LCD panel immediately after the activation (i.e. selection) of the row, as shown in FIG. 2A(b) and FIG. 2B (b). Since each of the LCD pixels in the row has a capacitance, they dissipate energy every time the voltage impressed upon them changes (due to the fact that then charging and discharging currents flow through them). The charging currents inevitably results in a further disadvantage that it causes a voltage drop due to the impedance of the LCD panel.
In portable apparatuses utilizing an LCD panel, the supply voltage is provided by a common battery, that the voltage drop pertinent to the LCD driving device, results in the voltage drops in other components such as display memory. In the conventional LCD driving device, the voltage drop can cause an erroneous display data read from the display memory 12, since display data is retrieved from the display memory 12 in the row selection period Tr1 and Tr2 but it is difficult to maintain a minimum necessary operational voltage for the read if such voltage drop takes place.